This invention relates to a memory circuit and, particularly, to a memory circuit suitably used for a frame buffer in a high-speed graphic display system.
Recent developments regarding enhanced resolution of graphic display units requires a large-capacity memory for use as a frame buffer for holding display information. In displaying a frame of graphic data, a great many access operations to a capacious frame buffer take place, and therefore high-speed memory read/write operations are required. A conventional method for coping with this requirement is the distribution of processing.
An example of the distributed process is to carry out part of the process with a frame buffer. FIG. 2 shows, as an example, the arrangement of the frame buffer memory circuit used in the conventional method. The circuit includes an operation unit 1, a memory 2, an operational function control register 3, and a write mask register 6. The frame buffer includes written data in bit units regardless of the word length of the memory device. On this account, the frame buffer writing process necessarily implements operation and writing both in bit units. In the example of FIG. 2, bit operation is implemented by the operation unit 1 and operational function control register 3, while bit writing is implemented by the mask register 6 only for bits effective for writing. This frame buffer is designed to implement the memory read-modify-write operation in the write cycle for data D from the data processor, eliminating the need for the reading data D0 out of the memory, which the usual memory necessitates in such operation, to thereby increase the speed of the frame buffer.
FIG. 3 shows another example of a distributed process which is applied to a graphic display system consisting of two data processors 10 and 10' linked through a common bus 11 with a frame buffer memory 9". The frame buffer memory 9" is divided into two areas a and b which are operated for display by the data processors 10 and 10', respectively. FIG. 4 shows an example of display made by this graphic system. The content of the frame buffer memory 9" is displayed on the CRT screen, which is divided into upper and lower sections in correspondence to the divided memory areas a and b as shown in FIG. 4. When it is intended to set up the memory 9" for displaying a circle, for example, the data processor 10 produces an arc .alpha..alpha.'.alpha." and the data processor 10' produces a remaining arc .beta..beta.'.beta." concurrently. The circular display process falls into two major processings of calculating the coordinates of the circle and writing the result into the frame buffer. When the calculation process takes a longer time than the writing process, use of the two processors 10 and 10' for the process is effective for increasing the speed of display. If, on the other hand, the writing process takes a longer time, the two processors conflict over the access to the frame buffer memory 9", resulting in a limited effectiveness of the dual processor system. Recently advanced LSI technology has significantly reduced the computation time of data processors relative to the memory write access time, which fosters use of a frame buffer memory requiring less access operations such as one 9' shown in FIG. 2.
In application of the frame buffer memory 9' shown in FIG. 2 to the display system shown in FIG. 3, when both processors share in the same display process as shown in FIG. 4, the memory modification function is consistent for both processors and no problems will arise. In another case, however, if one processor draws graphic display a' and another processor draws character display b' as shown in FIG. 5, the system is no longer so uneventful. In general, different kinds of display are accompanied by different memory modification operations, and if two processors alternately access the frame buffer memory, the setting for the modification operation and the read-modify-write operation need to take place in each display process. Setting for modification operation is identical to memory access when seen from the processor, and such double memory access ruins the attempt at increasing the processing speed.
A conceivable scheme for reducing the number of computational settings is the memory access control in which one processor makes access to the frame buffer several times and then hands over the access right to another processor, instead of the alternate memory access control. However, this method requires additional time for the process of handing over the access right between the processors as compared with the display process using a common memory modification function. Namely, the conventional scheme of sharing in the same process among more than one data processor as shown in FIG. 4 is recently shifting to the implementation of separate processes as shown in FIG. 5 with a plurality of data processors, as represented by the multi-window system, and the memory circuit is not designed in consideration of this regard.
An example of the frame buffer of this type using the read-modify-write operation is disclosed, for example, in article entitled "Designing a 1280-by-1024 pixel graphic display frame buffer in a 64K RAM with nibble mode", Nikkei Electronics, pp. 227-245, published on Aug. 27, 1984.